Sharing our vision for AI-driven chip design at KAIST

Prof. Mehdi Saligane visited KAIST to give the IEEE SSCS distinguished lecture "Rethinking Chip Design in the Age of AI."

AI is changing not only the applications we build, but also the way we design the chips that power them. This talk explores how we can rethink chip design in the age of AI from two complementary directions: using AI to automate and improve chip design, and building specialized chips that make AI dramatically more efficient.

On the design side, we present Agentic-RL gLayout, a reinforcement-learning framework for analog layout generation that replaces manual heuristics with goal-driven planning and self-correction. Built on open-source tools such as OpenROAD, gLayout, and OpenFASOC, it enables cleaner, more compact, and rule-compliant layouts with far less manual effort. On the architecture side, we present a hardware-software co-design stack for efficient edge AI, reducing latency and energy in LLM inference. By co-optimizing models, precision, and accelerator design, this approach supports fast, privacy-preserving inference under tight power constraints.

Taken together, these efforts illustrate a broader shift toward open, AI-enabled chip design flows and domain-specific AI hardware. The result is a faster, more automated, and more accessible path to silicon in the age of AI.

Many thanks to Prof. Wanyeong Jung and his students for hosting and for sharing their research thoughts on AI for chip design!